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128Mb: x4, x8, x16 DDR SDRAM
DOUBLE DATA RATE (DDR) SDRAM
* PC1600 and PC2100 compatible * VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V * Bi-directional data strobe (DQS) transmitted/ received with data, i.e., source-synchronous data capture (x16 has two - one per byte) * Internal, pipelined double-data-rate (DDR) architecture; two data accesses per clock cycle * Differential clock inputs (CK and CK#) * Commands entered on each positive CK edge * DQS edge-aligned with data for READs; center-aligned with data for WRITEs * DLL to align DQ and DQS transitions with CK * Four internal banks for concurrent operation * Data mask (DM) for masking write data (x16 has two - one per byte) * Programmable burst lengths: 2, 4, or 8 * Auto precharge option * Auto Refresh * Longer lead TSOP for improved reliability (OCPL) * 2.5V I/O (SSTL_2 compatible)
Timing - Cycle Time 7.5ns @ CL = 2.5 (PC2100) 10ns @ CL = 2.5 (PC1600) Part number example:
(For part numbers prior to December 2004, refer to page 13 for decoding.)
-75A -8A
SAA16M8T95AV4TL-75A
Options:
Family SpecTek Memory Configuration 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 banks) Design ID DDR 128 Megabit Design (Call SpecTek Sales for details on availability of "x" placeholders) Voltage and refresh 2.5V, Auto Refresh 2.5V, Self or Auto Refresh Plastic Package - OCPL 66-pin TSOP (400 mil width, 0.65mm pin pitch)
Designation:
SAA 32M4 16M8 8M16
Yx6x
V4 R4
TL
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128Mb: x4, x8, x16 DDR SDRAM
GENERAL DESCRIPTION
The 128Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 134,217,728 bits. It is internally configured as a quad-bank DRAM. The 128Mb DDR SDRAM uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 2n-prefetch architecture with an interface designed to transfer two data words per clock cycle at the I/O pins. A single read or write access for the 128Mb DDR SDRAM effectively consists of a single 2n-bit wide, one-clock-cycle data transfer at the internal DRAM core and two corresponding n-bit wide, one-half-clock-cycle data transfers at the I/O pins. A bi-directional data strobe (DQS) is transmitted externally, along with data, for use in data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during READs and by the memory controller during WRITEs. DQS is edge-aligned with data for READs and center-aligned with data for WRITEs. The x16 offering has two data strobes, one for the lower byte and one for the upper byte. The 128Mb DDR SDRAM operates from a differential clock (CK and CK#); the crossing of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK. Commands (address and control signals) are registered at every positive edge of CK. Input data is registered on both edges of DQS, and output data is referenced to both edges of DQS, as well as to both edges of CK. Read and write accesses to the DDR SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of an ACTIVE command, which is then followed by a READ or WRITE command. The address bits registered coincident with the ACTIVE command are used to select the bank and row to be accessed. The address bits registered coincident with the READ or WRITE command are used to select the bank and the starting column location for the burst access. The DDR SDRAM provides for programmable READ or WRITE burst lengths of 2, 4, or 8 locations. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDR SDRAMs, the pipelined, multibank architecture of DDR SDRAMs allows for concurrent operation, thereby providing high effective bandwidth by hiding row precharge and activation time. An auto refresh mode is provided, along with a powersaving power-down mode. All inputs are compatible with the JEDEC Standard for SSTL_2. All full drive strength outputs are SSTL_2, Class II compatible.
NOTE 1: The functionality and the timing specifications discussed in this data sheet are for the DLL-enabled mode of operation. NOTE 2: Throughout the data sheet, the various figures and text refer to DQs as "DQ." The DQ term is to be interpreted as any and all DQ collectively, unless specifically stated otherwise. Additionally, the x16 is divided in to two bytes -- the lower byte and upper byte. For the lower byte (DQ0 through DQ7) DM refers to LDM and DQS refers to LDQS; and for the upper byte (DQ8 through DQ15) DM refers to UDM and DQS refers to UDQS.
___________________________________________________
ABSOLUTE MAXIMUM RATINGS*
VDD Supply Voltage Relative to VSS .....................................-1V to +3.6V VDDQ Supply Voltage Relative to VSS ......................... -1V to +3.6V VREF and Inputs Voltage Relative to VSS .....................................-1V to +3.6V I/O Pins Voltage Relative to VSS ..........................-0.5V to VDDQ +0.5V Operating Temperature, TA (ambient) ......... 25C to +70C Storage Temperature (plastic) ................. -55C to +150C Power Dissipation ..................................................1W Short Circuit Output Current ..................................50mA
Disclaimer: Except as specifically provided in this document, SpecTek makes no warranties, expressed or implied, including, but not limited to, any implied warranties of merchantability or fitness for a particular purpose. Any claim against SpecTek must be made within 1 year from the date of shipment from SpecTek, and SpecTek has no liability thereafter. Any liability is limited to replacement of the defective items or return of amounts paid for defective items (at buyer's election). In no event will SpecTek be responsible for special, indirect, consequential or incidental damages, even if SpecTek has been advised for the possibility of such damages. SpecTek's liability from any cause pursuant to this specification shall be limited to general monetary damages in an amount not to exceed the total purchase price of the products covered by this specification, regardless of the form in which legal or equitable action may be brought against SpecTek.
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DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS
(25C < TA < +70C; VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V)
PARAMETER/CONDITION Supply Voltage I/O Supply Voltage I/O Reference Voltage I/O Termination Voltage (system) Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Clock Input Voltage Level; CK and CK# Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# INPUT LEAKAGE CURRENT Any input, 0V < VIN < VDD, VREF pin 0V < VIN < 1.35V (All other pins not under test = 0V) OUTPUT LEAKAGE CURRENT (DQs are disabled; 0V < VOUT < VDDQ) OUTPUT LEVELS: Full drive option - x4 , x8, x16 High Current (VOUT = VDDQ-0.373V, minimum VREF, minimum VTT) Low Current (VOUT = 0.373V, maximum VREF,maximum VTT) OUTPUT LEVELS: Reduced drive option - x16 only High Current (VOUT = VDDQ-0.763V, minimum VREF, minimum VTT) Low Current (VOUT = 0.763V, maximum VREF,maximum VTT)
SYMBOL
VDD VDDQ
MIN 2.3 2.3 0.49 X VDDQ VREF - 0.04 VREF + 0.15 -0.3 -0.3 0.36 1.15 -2
MAX 2.7 2.7 0.51 X VDDQ VREF - 0.04 VDD + 0.3 VREF - 0.15 VDDQ + 0.3 VDDQ + 0.6 1.35 2
UNITS V V V V V V V V V A
NOTES 41 41, 44 6, 44 7, 44 28 28 8 9
VREF VTT VIH (DC) VIL (DC) VIN VID VIX II
IOZ IOH IOL
-7 -16.8 16.8
7 ---
A mA mA 37, 39
IOHR IOLR
-9 9
---
mA mA
38, 39
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128Mb: x4, x8, x16 DDR SDRAM
AC INPUT OPERATING CONDITIONS
(25C < TA < + 70C; VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V)
PARAMETER/CONDITION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Clock Input Differential Voltage; CK and CK# Clock Input Crossing Point Voltage; CK and CK# I/O Reference Voltage
SYMBOL VIH (AC) VIL (AC) VID (AC) VIX (AC) VREF (AC)
MIN VREF + 0.310 -0.7 0.5 X VDDQ - 0.2 0.49 X VDDQ
MAX -VREF - 0.310 VDDQ + 0.6 0.5 X VDDQ + 0.2 0.51 X VDDQ
UNIT S V V V V V
NOTES 14, 28, 40 14, 28, 40 8 9 6
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CAPACITANCE (x4, x8)
(25C < TA < +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
PARAMETER Delta Input/Output Capacitance: DQs, DQS, DM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Delta Input Capacitance: DQs, DQS, DM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE
SYMBOL DCIO DCI1 DCI2 CIO CI1 CI2 CI3
MIN ---4.0 2.0 2.0 2.0
MAX 0.50 0.50 0.25 5.0 3.0 3.0 3.0
UNITS pF pF pF pF pF pF pF
NOTES 24 29 29
IDD SPECIFICATIONS AND CONDITIONS (x4, x8)
(25C < TA < +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
PARAMETER/CONDITION OPERATING CURRENT: One bank; Active-Precharge; RC = RC (MIN); t CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; t RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK(MIN); CKE=LOW; IDLE STANDBY CURRENNT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = t CK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = t CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t AUTO REFRESH CURRENT RC = tRFC (MIN) SELF REFRESH CURRENT (Part number `R' only) OPERATING CURRENT: Four bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tRC (MIN); Address and control inputs change only during Active, READ, or WRITE commands.
t t
SYMBOL IDD0
-75 105
-8 100
UNITS mA
NOTES 22, 48
IDD1
120
115
mA
22, 48
IDD2P IDD2N
10 50
10 45
mA mA
23, 32, 50 51
IDD3P IDD3N
18 50
18 45
mA mA
23, 32, 50 22
IDD4R
120
110
mA
22, 48
IDD4W
120
110
mA
22
IDD5 IDD7 IDD8
250 2 330
225 2 285
mA mA mA
22, 50 11 22, 49
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CAPACITANCE (x16)
(25C < TA < +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
PARAMETER Delta Input/Output Capacitance: DQ0 - DQ7, LDQS, LDM Delta Input/Output Capacitance: DQ8-DQ15, UDQS, UDM Delta Input Capacitance: Command and Address Delta Input Capacitance: CK, CK# Input/Output Capacitance: DQs, LDQS, UDQS, LDM, UDM Input Capacitance: Command and Address Input Capacitance: CK, CK# Input Capacitance: CKE
SYMBOL DCIOL DCIOU DCI1 DCI2 CIO CI1 CI2 CI3
MIN ----4.0 2.0 2.0 2.0
MAX 0.50 0.50 0.50 0.25 5.0 3.0 3.0 3.0
UNITS pF pF pF pF pF pF pF pF
NOTES 24 24 29 29
IDD SPECIFICATIONS AND CONDITIONS (x16)
(25C < TA < +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
PARAMETER/CONDITION OPERATING CURRENT: One bank; Active-Precharge; RC = RC (MIN); t CK = tCK (MIN); DQ, DM, and DQS inputs changing once per clock cycle; Address and control inputs changing once every two clock cycles; OPERATING CURRENT: One bank; Active-Read-Precharge; Burst = 2; t RC = tRC (MIN); tCK = tCK (MIN); IOUT = 0mA; Address and control inputs changing once per clock cycle PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle; Power-down mode; tCK = tCK(MIN); CKE=LOW; IDLE STANDBY CURRENNT: CS# = HIGH; All banks idle; tCK = tCK (MIN); CKE = HIGH; Address and other control inputs changing once per clock cycle. VIN = VREF for DQ, DQS, and DM ACTIVE POWER-DOWN STANDBY CURRENT: One bank active; Power-down mode; tCK = tCK (MIN); CKE = LOW ACTIVE STANDBY CURRENT: CS# = HIGH; CKE = HIGH; One bank; Active-Precharge; tRC = tRAS (MAX); tCK = tCK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle; Address and other control inputs changing once per clock cycle. OPERATING CURRENT: Burst = 2; Reads; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = t CK (MIN); IOUT = 0mA OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One bank active; Address and control inputs changing once per clock cycle; tCK = t CK (MIN); DQ, DM, and DQS inputs changing twice per clock cycle t AUTO REFRESH CURRENT RC = tRFC (MIN) SELF REFRESH CURRENT (Part number `R' only) OPERATING CURRENT: Four bank interleaving READs (BL = 4) with auto precharge, tRC = tRC (MIN); tCK = tRC (MIN); Address and control inputs change only during Active, READ, or WRITE commands.
t t
SYMBOL IDD0
-75 115
-8 105
UNITS mA
NOTES 22, 48
IDD1
140
115
mA
22, 48
IDD2P IDD2N
10 50
10 45
mA mA
23, 32, 50 51
IDD3P IDD3N
18 50
18 45
mA mA
23, 32, 50 22
IDD4R
170
160
mA
22, 48
IDD4W
150
145
mA
22
IDD5 IDD7 IDD8
255 2 330
225 2 285
mA mA mA
22, 50 11 22, 49
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(25C < TA < +70C; VDDQ = +2.5V 0.2V, VDD = +2.5V 0.2V)
AC CHARACTERISTICS PARAMETER Access window of DQs from CK/CK# CK high-level width CK low-level width Clock cycle time CL = 2.5 DQ and DM input hold time relative to DQS DQ and DM input setup time relative to DQS DQ and DM input pulse width (for each input) Access window of DQS from CK/CK# DQS input high pulse width DQS input low pulse width DQS-DQ skew, DQS to last DQ valid, per group, per access DQS-DQ skew, first DQS to last DQ valid, per access Write command to first DQS latching transition DQS falling edge to CK rising - setup time DQS falling edge from CK rising - hold time Half clock period Data-out high-impedance window from CK/CK# Data-out low-impedance window from CK/CK# Address and control input hold time (fast slew rate) Address and control input setup time (fast slew rate) Address and control input hold time (slow slew rate) Address and control input setup time (slow slew rate) LOAD MODE REGISTER command cycle time DQ-DQS hold, DQS to first DQ to go non-valid, per access Data hold skew factor ACTIVE to PRECHARGE command ACTIVE to READ with Auto precharge command ACTIVE to ACTIVE/AUTO REFRESH command period AUTO REFRESH command period ACTIVE to READ or WRITE delay PRECHARGE command period DQS read preamble DQS read postamble ACTIVE bank a to ACTIVE bank b command SYMBOL AC CH t CL t CK (2.5)
t t
-75 MIN -0.75 0.45 0.45 7.5 0.5 0.5 1.75 -0.75 0.35 0.35 MAX +0.75 0.55 0.55 12 MIN -0.8 0.45 0.45 10 0.6 0.6 2 -0.8 0.35 0.35
-8 MAX +0.8 0.55 0.55 12 UNITS ns CK t CK ns
t
NOTES 30 30 52 26, 31 26, 31 31
DH DS t DIPW t DQSCK t DQSH t DQSL t DQSQ
t t
t
+0.75
+0.8
0.5 0.7 1.25
0.6 0.8 1.25
ns ns ns ns t CK t CK ns ns CK t CK t CK ns
t
25, 26 36
DQSQA t DQSS t DSS t DSH t HP HZ LZ t IHf t ISf t IHs t ISs t MRD t QH
t t t
0.75 0.2 0.2 t CH, t CL -0.75 -0.75 .90 .90 1 1 15 tHP tQHS 45 65 75 20 20 0.9 0.4 15
+0.75 +0.75
0.75 0.2 0.2 t CH, t CL -0.8 -0.8 1.1 1.1 1.1 1.1 16 tHP tQHS 50 70 80 20 20 0.9 0.4 15
34 18 18 14 14 14 14 25, 26
+0.8 +0.8
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t CK t CK ns
QHS RAS t RAP t RC
t t
0.75 16,000
1 16,000
35 46
RFC RCD t RP t RPRE t RPST t RRD
t
50
1.1 0.6
1.1 0.6
42
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ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS, (continued)
AC CHARACTERISTICS PARAMETER DQS write preamble DQS write preamble setup time DQS write postamble Write recovery time Internal WRITE to READ command delay Data valid output window REFRESH to REFRESH command interval Average periodic refresh interval Terminating voltage delay to Vdd
Exit SELF REFRESH to non-READ command (Part number R only) Exit SELF REFRESH to READ command (Part number R only)
-75 SYMBOL
t
-8 MIN MAX UNITS
t
MIN
MAX
NOTES 20, 21 19
WPRE WPRES t WPST t WR t WTR na t REFC t REFI t VTD t XSNR
t
t
0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 15.6 0 75 200
0.25 0 0.4 0.6 15 1 tQH - tDQSQ 140.6 15.6 0 80 200
CK ns t CK ns t CK ns s s ns ns
t
25 23 23
XSRD
CK
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NOTES
1. All voltages referenced to VSS. 2. Tests for AC timing, IDD, and electrical AC and DC characteristics may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Outputs measured with equivalent load: properly initialized, and is averaged at the defined cycle rate. 11. Enables on-chip refresh and address counters. 12. IDD specifications are tested after the device is properly initialized, and is averaged at the defined cycle rate. 13. This parameter is sampled. VDD = +2.5V 0.2V, VDDQ = +2.5V 0.2V, VREF = VSS, f = 100 MHz, TA = 25C, VOUT(DC) = VDDQ/2, VOUT (peak to peak) = 0.2V. DM input is grouped with I/O pins, reflecting the fact that they are matched in loading. 14. Command/Address input slew rate = 0.5V/ns. For -7 and -75 with slew rates 1V/ns and faster, t IS and tIH are reduced to 900ps. If the slew rate is less than 0.5V/ns, timing must be derated: tIS has an additional 50ps per each 100mV/ns reduction in slew rate from the 500mV/ns. tIH has 0ps added, that is, it remains constant. If the slew rate exceeds 4.5V/ns, functionality is uncertain. 15. The CK/CK# input reference level (for timing referenced to CK/CK#) is the point at which CK and CK# cross; the input reference level for signals other than CK/CK# is VREF. 16. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE < 0.3 x VDDQ is recognized as LOW. 17. The output timing reference level, as measured at the timing reference point indicated in Note 3, is VTT. 18. tHZ and t LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level, but specify when the device output is no longer driving (HZ) or begins driving (LZ). 19. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but system performance (bus turnaround) will degrade accordingly. 20. This is not a device limit. The device will operate with a negative value, but system performance could be degraded due to bus turnaround. 21. It is recommended that DQS be valid (HIGH or LOW) on or before the WRITE command. The case shown (DQS going from High-Z to logic LOW) applies when no WRITEs were previously in progress on the bus. If a previous WRITE was in progress, DQS could be HIGH during this time, depending on tDQSS. 9
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4. AC timing and IDD tests may use a VIL- to-VIH swing of up to 1.5V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK#), and parameter specifications are guaranteed for the specified AC input levels under normal use conditions. The minimum slew rate for the input signals used to test the device is 1V/ns in the range between VIL(AC) and VIH(AC). 5. The AC and DC input level specifications areas defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the AC input level, and will remain in that state as long as the signal does not ring back above [below] the DC input LOW [HIGH] level). 6. VREF is expected to equal VDDQ/2 of the transmitting device and to track variations in the DC level of the same. Peak-to-peak noise (noncommon mode) on VREF may not exceed 2 percent of the DC value. Thus, from VDDQ/2, VREF is allowed 25mV for DC error and an additional 25mV for AC noise. 7. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF and must track variations in the DC level of VREF. 8. VID is the magnitude of the difference between the input level on CK and the input level on CK#. 9. The value of Vix is expected to equal VddQ/2 of the transmitting device and must track variations in the DC level of the same. 10. Idd is dependent on output loading and cycle rates. Specified values are obtained with minimum cycle time at CL = 2.5 for -7.5 and -8 with the outputs open.
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128Mb: x4, x8, x16 DDR SDRAM
NOTES, continued
22. MIN ( tRC or tRFC) for IDD measurements is the smallest multiple of tCK that meets the minimum absolute value for the respective parameter. tRAS (MAX) for IDD measurements is the largest multiple of tCK that meets the maximum absolute value for tRAS. 23. The refresh period 64ms. This equates to an average refresh rate of 15.625s. However, an AUTO REFRESH command must be asserted at least once every 140.6s; burst refreshing or posting by the DRAM controller greater than eight refresh cycles is not allowed. 24. The I/O capacitance per DQS and DQ byte/group will not differ by more than this maxi-or mum amount for any given device. 25. The valid data window is derived by achieving other specifications - tHP ( tCK/2), tDQSQ, and t QH ( tQH = tHP - tQHS). The data valid window derates directly proportional with the clock duty cycle and a practical data valid window can be derived. The clock is allowed a maximum duty cycle variation of 45/55. Functionality is uncertain when operating beyond a 45/55 ratio. The data valid window derating curves are provided below for duty cycles ranging between 50/50 and 45/55. 26. Referenced to each output group: x4 = DQS with DQ0-DQ3; x8 = DQS with DQ0-DQ7; x16 = LDQS with DQ0-DQ7 and UDQS with DQ8DQ15. 27. This limit is actually a nominal value and does not result in a fail value. CKE is HIGH during REFRESH command period ( tRFC [MIN]) else CKE is LOW (i.e., during standby). 28. To maintain a valid level, the transitioning edge of the input must: a) Sustain a constant slew rate from the Current AC level through to the target AC level, VIL(AC) VIH(AC). b) Reach at least the target AC level. c) After the AC target level is reached, continue to maintain at least the target DC level, VIL(DC) or VIH(DC). 29. The Input capacitance per pin group will not differ by more than this maximum amount for any given device. 30. CK and CK# input slew rate must be >1V/ns. 31. DQ and DM input slew rates must not deviate from DQS by more than 10%. If the DQ/DM/DQS slew rate is less than 0.5V/ns, timing must be derated: 50ps must be added to tDS and tDH for each 100mv/ns reduction in slew rate. If slew rate exceeds 4V/ns, functionality is uncertain. 32. VDD must not vary more than 4% if CKE is not active while any bank is active. 33. The clock is allowed up to 150ps of jitter. Each timing parameter is allowed to vary by the same amount. 34. tHP min is the lesser of tCL minimum and tCH minimum actually applied to the device CK and CK/ inputs, collectively during bank active. 35. READs and WRITEs with auto precharge are not allowed to be issued until tRAS (MIN) can be satisfied prior to the internal precharge command being issued. 36. Applies to x16 only. First DQS (LDQS or UDQS) to transition to last DQ (DQ0-DQ15) to transition valid. Initial JEDEC specifications suggested this to be same as tDQSQ. 37. Note 37 is not used. 38. Note 38 is not used. 39. Note 39 is not used. 40. VIH overshoot: VIH(MAX) = VDDQ+1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. VIL undershoot: VIL(MIN) = -1.5V for a pulse width < 3ns and the pulse width can not be greater than 1/3 of the cycle rate. 41. VDD and VDDQ must track each other. 42. Note 42 is not used. 43. Note 43 is not used. 44. During initialization, VddQ, Vtt, and Vref must be equal to or less than Vdd + 0.3V. Alternatively, Vtt may be 1.35V maximum during power up, even if Vdd /VddQ are 0 volts, provided a minimum of 42 ohms of series resistance is used between the Vtt supply and the input pin.
PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004
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128Mb: x4, x8, x16 DDR SDRAM
REFRESH command is registered, CKE must be active at each NOTES, continued rising clock edge, until tREF later. 45. Note 45 is not used. 51. IDD2N specifies the DQ, DQS, and DM to be 46. tRAP > tRCD. driven to a valid high or low logic level. IDD2Q is 47. Note 47 is not used. similar to IDD2F except IDD2Q specifies the 48. Random addressing changing 50% of data address and control inputs to remain stable. changing at every transfer. Although IDD2F, IDD2N, and IDD2Q are similar, 49. Random addressing changing 100% of data IDD2F is "worst case." changing at every transfer. 52. 50. CKE must be active (high) during the entire time a refresh Whenever the operating frequency is altered, not command is executed. That is, from the time the AUTO including jitter, the DLL is required to be reset. This is followed by 200 clock cycles.
PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 DDR SDRAM
PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004
12
www.spectek.com
SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek
128Mb: x4, x8, x16 DDR SDRAM
PART NUMBERS FOR PRODUCT PRIOR TO DECEMBER 2004 OPTIONS
* Configuration 32 Meg x 4 (8 Meg x 4 x 4 banks) 16 Meg x 8 (4 Meg x 8 x 4 banks) 8 Meg x 16 (2 Meg x 16 x 4 banks) Voltage and refresh 2.5V, Auto Refresh 2.5V, Self or Auto Refresh Parent Device Configuration 32 Meg x 4 16 Meg x 8 8 Meg x 16 Plastic Package - OCPL 66-pin TSOP (400 mil width, 0.65mm pin pitch) Timing - Cycle Time 7.5ns @ CL = 2.5 (PC2100) 10ns @ CL = 2.5 (PC1600)
MARKING
S40032 S80016 S16008 VH RH 8 7 9 TW
* *
* *
-75A -8A
(Example part number: S80016VH7TW-75A)
http://www.spectek.com/menus/part_guides.asp
PDF: 09005aef80505d1b / Source: 09005aef80469e44 128Mb: x4, x8, x16 DDR SDRAM Rev: 11/23/2004
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SpecTek reserves the right to change products or specifications without notice. (c) 2001, 2002, 2004 SpecTek

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